FIG. 12 illustrates a schematic cross sectional view of an electronic device of the related art. An electronic device 81 includes an electronic element package 82 and an interconnection substrate 92. The electronic element package 82 is obtained on mounting an electronic element 83 on an interposer substrate 85 and sealing the resulting assembly with an encapsulation resin 84. The interconnection substrate 92 has mounted thereon the electronic element package 82. The electronic element package 82 and the interconnection substrate 92 are electrically connected to each other via an electrical connection part 93. The electrical connection part 93 is formed by electrically connecting a package electrode for electrical connection 86 of the electronic element package 82 and a substrate electrode 90 of the interconnection substrate 92 via solder bumps 88.
The electronic element 83 is packaged on the interposer substrate 85 by, for example, flip chip packaging in which an electrode of the electronic element 83 and an electrode of the interposer substrate 85 are electrically connected to each other via e.g., solder bumps.
In the electronic device 81, shown in FIG. 12, the coefficients of thermal expansion of the electronic element 83, the interposer substrate 85 and the interconnection substrate 92 differ in general from one another. Hence, if the temperature of the electronic element 83, the interposer substrate 85 and the interconnection substrate 92 is elevated due to heat evolution during use or to heating during the manufacturing process, the respective components undergo differential thermal expansion and contraction. As a result, the electrical connection part 93 (solder bump connection) between the electronic element 83, the interposer substrate 85 and the interconnection substrate 92 is susceptible to cracking due to warp caused by the differential thermal expansion or contraction.
Recently, the shifting from tin lead solder to lead-free solder is going on rapidly under environmental regulations. The melting temperature of tin lead eutectic solder composed of, for example, 63 wt % of Sn, with the balance being Pb, is 183° C., whereas that of lead-free solder, composed mainly of tin and also including, for example, silver, copper, zinc, bismuth, indium, antimony, nickel and germanium, is high and is in a range of 190° C. to 230° C. Viz., if the lead-free solder is used, the packaging temperature is higher by 20° C. to 30° C. than if the tin lead solder is used. Hence, the risk of cracking is higher with the use of the lead-free solder.
The technique of enhancing the connection reliability between the electronic element package and the interconnection substrate or that between the electronic element and the interposer is disclosed in Patent Documents 1 to, for example.
The semiconductor device disclosed in Patent Document 1 includes an interconnection layer formed on a substrate or on an IC chip, electrode connection bumps connected to the interconnection layer and arranged on the substrate or on the IC chip, and dummy connection bumps arranged outside the electrode connection bumps and adapted for moderating the stress applied to the electrode connection bumps.
An interconnection substrate disclosed in Patent Document 2 is such an interconnection substrate in which an interconnection conductor is arranged in the inside of a square-shaped insulation substrate of ceramics. A large number of connection pads, electrically connected to interconnection conductors, are formed on the major surface of the insulation substrate. There are two sorts of the connection pads, namely first connection pads formed in a square-shaped pattern along the outer rim of the insulation substrate and second connection pads formed in a lattice pattern in a square-shaped center region of the insulation substrate. Four elliptically-shaped reinforcement dummy pads whose longitudinal axis extends towards the center of the insulation substrate are provided on the major surface of the insulation substrate between the pads arranged at angular parts of the square-shaped array of the first connection pads and the pads arranged at angular parts of the radially outermost lattice array of the second connection pads.
A semiconductor device disclosed in Patent Document 3 is such a semiconductor device in which a semiconductor element is mounted in a face-down configuration on a major surface of a substrate by flip chip packaging, with bumps arranged in-between. A real electrode pad of the semiconductor element and a real electrode terminal of the substrate are interconnected by solder bumps. A plurality of dummy electrode pads are provided on the semiconductor element and a plurality of dummy electrode terminals are provided on the substrate in association with the dummy electrode pads. The dummy electrode pads and the dummy electrode terminals are interconnected by gold bumps.
A semiconductor package, disclosed in Patent Document 4, is such a semiconductor package in which a set of solder bumps for mounting semiconductor components are formed on an interconnection substrate. The solder bumps are formed by providing a solder material on connection pads formed of metal conductors, and a resin spacer for providing the spacing between a semiconductor component and the connection pad is provided within the region of the solder bumps.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2004-200197A    [Patent Document 2] JP Patent Kokai Publication No. JP-P2004-281473A    [Patent Document 3] JP Patent Kokai Publication No. JP-A-10-154726    [Patent Document 4] JP Patent Kokai Publication No. JP-A-10-13012